1. Field of the Invention
This invention relates to a semiconductor memory device with a built-in self-diagnostic function and a semiconductor device having this semiconductor memory device. Particularly, this invention relates to a semiconductor memory device having a self-diagnostic test function which enables flexible adjustment to a change of test specification.
2. Description of the Related Art
To test a recent large-capacity high-speed semiconductor memory device, a tester needs to operate at a high speed. Particularly a tester necessary for testing a high-speed synchronous semiconductor memory device is required to operate at a very high speed and the tester itself is expensive. Moreover, depending on increase in operation frequency of the semiconductor memory device, the tester cannot follow the increased operation frequency.
As systems have become more and more advanced and complicated, a built-in semiconductor memory device with a large capacity is provided as a memory module in a high-performance semiconductor device called system LSI. In some cases, for such a semiconductor memory device as a built-in module, a terminal group for inputting/outputting addresses, data, commands and the like is not provided as a terminal group of the semiconductor device and testing of the semiconductor memory device cannot be carried out from the outside.
Thus, if a built-in self-test (hereinafter referred to as BIST) circuit for carrying out self-diagnosis of the memory is provided in the semiconductor memory device or in the semiconductor device having the semiconductor memory device as a memory module, testing can be carried out without using an expensive tester for the large-capacity high-speed semiconductor memory device and irrespective of the presence/absence of a test terminal for the memory module built-in the semiconductor device.
As an example of the semiconductor memory device having such a BIST circuit, a semiconductor memory device is described in the JP Laid-Open Patent Publication No.2001-148199, in which a program for carrying out self-test loaded in advance in a command RAM 50 is sequentially read out in accordance with a program counter value outputted from an ALPG 54, thus testing a memory-cell array 30, and the test result is outputted via an input/output and BIST write/judgment circuit 32, as shown in FIG. 18. The loading of the program to the command RAM 50 is carried out as a BIST controller 62 functions as a load sequencer for the program. It is a semiconductor memory device in which testing is carried out while changing data and command patterns by loading the program for test to the command RAM 50 from the outside.
However, in the case where testing by a BIST circuit built in a semiconductor memory device or a memory module of a semiconductor device constituted on the basis of memory specifications established at the time of design, if the number of types of write data patterns to each memory cell by BIST increases, the circuit scale of the BIST circuit expands and the proportion of the BIST circuit region to a memory main circuit region which functions as a semiconductor memory device, on a chip die, increases, as shown in FIG. 16. Therefore, increase in overhead due to the occupied area of the BIST circuit on the chip causes a problem of increase in chip size and chip cost.
In the case where a built-in semiconductor memory device is provided as a memory module in a semiconductor device, generally, the required memory capacity differs depending on the specifications of a system in which the semiconductor device is used. Thus, in expanding types of semiconductor device, in order to reduce the time and cost for development and manufacture, a memory module is designed in accordance with a maximum memory capacity required for the type expansion and only module structures such as memory capacity, address length, bus width, burst length that are necessary for individual types are used.
In this case, however, the test specifications of the BIST circuit need be adjusted to each of the actually used memory modules. Memory modules having a maximum permissible memory capacity must be provided and the BIST circuit must be redesigned for each type despite the reduction in time and cost for redevelopment and remanufacture of the memory modules, which is a problem. For example, as shown in FIG. 17, if two megabits are used for an eight-megabit memory module as a memory main circuit, a BIST circuit for two megabits (FIG. 17, (A)) is necessary. A BIST circuit for four megabits (FIG. 17, (B)) is necessary in the case of four megabits, and a BIST circuit for eight megabits (FIG. 17, (C)) is necessary in the case of eight megabits. Moreover, with respect to the bus width, a BIST circuit for xc3x978 bits (FIG. 17, (D)) is necessary in the case of xc3x978 bits. A BIST circuit for xc3x9716 bits (FIG. 17, (E)) is necessary in the case of xc3x9716 bits, and a BIST circuit for xc3x9732 bits (FIG. 17, (F)) is necessary in the case of xc3x9732 bits.
Once the BIST circuit is installed, its operation specifications cannot be changed, causing a problem that change and addition of write data patterns and change of the test specifications cannot be carried out.
The change of the test specifications in the BIST circuit is possible by using a semiconductor memory device described in the JP Laid-Open Patent Publication No.2001-148199. However, in the semiconductor memory device of the JP Laid-Open Patent Publication No.2001-148199, the command RAM 50 made of an SRAM, the ALPG 54 and the like must be provided for storage of programs, operation control and the like. Therefore, the BIST circuit needs complicated control. There arise problems such as a longer development period due to the complicated circuit structure and increase in overhead on the chip die due to the need for a large occupied area on the chip.
In order to solve at least one of the problems of the above-described conventional techniques, it is an object of the present invention to provide a semiconductor memory device having a self-diagnostic test function which enables flexible adjustment to change and addition of test specifications without having a complicated and large-scale circuit structure to perform complicated control in self-diagnostic test, or to provide a semiconductor device having the semiconductor memory device as a memory macro.
In order to achieve the above-described object, a semiconductor memory device or a semiconductor device having a semiconductor memory device as a memory macro according to one aspect of the present invention includes a semiconductor memory device having a self-diagnostic test function, the semiconductor memory device comprising a memory operation specification information storing unit in which memory operation specification information that is rewritable from the outside is stored, wherein an operation parameter in self-diagnostic test is set on the basis of the memory operation specification information.
A semiconductor memory device or a semiconductor device having a semiconductor memory device as a memory macro according to another aspect of the present invention includes a semiconductor memory device having a self-diagnostic test function, the semiconductor memory device comprising a test specification information storing unit in which test specification information that is rewritable from the outside is stored, wherein operation specification in self-diagnostic test is set on the basis of the test specification information.
In the semiconductor memory device or the semiconductor device having a semiconductor memory device as a memory macro according to one aspect or another aspect of the present invention, a memory operation specification information storing unit in which memory operation information that is rewritable from the outside is stored, or a test specification information storing unit in which test specification information that is rewritable from the outside is stored, is provided and an operation parameter or operation specification in self-diagnostic test is set on the basis of each information stored in each storing unit.
Thus, since the memory operation specification information can be properly rewritten from the outside the semiconductor memory device, the memory operation specification information can be rewritten in accordance with each type in expanding the types of the semiconductor memory device and the self-diagnostic test function need not be redesigned for each type.
Moreover, since the test specification information can be properly rewritten from the outside the semiconductor memory device, even when the number of test items is increased, the test specification information can be rewritten for each test and the increased number of test items can be dealt with by using a compact self-diagnostic test structure. Also in the case of change or addition of the test specifications, the test specification information can be rewritten in accordance with the test specifications and the self-diagnostic test function need not be redesigned.
Furthermore, as the memory operation specification information or the test specification information is rewritten when necessary, variation elements such as increase in the number of test items, change and addition of the test specifications, and type expansion can be dealt with by one type of self-diagnostic test structure. Therefore, complicated control such as loading a program for each variation element is no longer necessary.
In a test circuit which realizes the self-diagnostic test function, the circuit scale of the test circuit is not increased by the increase in number of test items, and redesign of the test circuit due to change or addition of the test specifications or corresponding to each type of semiconductor memory device is not necessary. Moreover, a complicated large-scale circuit structure to deal with all the variation elements such as increase in the number of test items, change and addition of the test specifications, and type expansion, is not necessary, either. The period for development and design of the self-diagnostic test circuit can be shortened. At the same time, the occupied area of the test circuit in the semiconductor memory device can be reduced to a small area and increase in chip size and chip cost can be restrained.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.